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EMIF09-SD01F3
9-line IPADTM, EMI filter and ESD protection
Features

9-line EMI low-pass filter and ESD protection High efficiency in EMI filtering Lead-free package 400 m pitch Very low PCB space occupation: < 4 mm2 Very thin package: 0.6 mm High reliability offered by monolithic integration Reduction of parasitic elements thanks to CSP integration Figure 1. Pin layout (bump side)
5 4 3 2 1 A B C D E
Flip Chip 24 bumps
Complies with the following standards
IEC61000-4-2 level 4 on external pins: - 15 kV (air discharge) - 8 kV (contact discharge) IEC61000-4-2 level 2 on internal pins: - 2 kV (air discharge) - 2 kV (contact discharge) MIL STD 883F - Method 3015.7 Class 3
Application
Secure digital memory card in mobile phones and communication systems
Description
The EMIF09-SD01F3 is a highly integrated array designed to suppress EMI/RFI noise for secure digital memory cards. The EMIF09-SD01F3 is in a Flip Chip package to offer space saving and high RF performance. This low-pass filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 15 kV. This filter also has a low line capacitance to be compatible with high data rate signals.
TM: IPAD is a trademark of STMicroelectronics.
April 2008
Rev 4
www.st.com
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Characteristics
EMIF09-SD01F3
1
Characteristics
Figure 2.
DAT3_PU
Device configuration
VSD
R11
R13 R12 R14
R15
CLK CMD DATA0 DATA1 DATA2 DATA3 CD WP WP+CD DAT3_PD R21 R8 R6 R4 R2
R1 R3 R5 R7 R9
SDCLK SDCMD SDDATA0 SDDATA1 SDDATA2 SDDATA3 SDCD SDWP SDWP+CD
GND_H
GND_C
Table 1.
Pin-signal attribution
Pin Description Pin Description Pin Description Pin Description Pin Description A1 A2 A3 A4 A5 DATA2 DATA3 GND_H SDDATA2 SDDATA3 B1 B2 B3 B4 B5 SDCD SDCMD CD CMD C1 C2 C3 C4 C5 DAT3_PD WP DAT3_PU SDWP VSD D1 D2 D3 D4 D5 WP+CD CLK GND_C SDWP+CD SDCLK E1 E2 E3 E4 E5 DATA1 DATA0 GND_C SDDATA1 SDDATA0
Table 2.
Symbol
Absolute ratings (limiting values)
Parameter Internal pins (A1, B1, C1, D1, E1, A2, B2, C2, D2, E2, C3) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge External pins (A4, B4, C4, D4, E4, A5, B5, C5, D5, E5) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge Junction temperature Operating temperature range Storage temperature range Value Unit
VPP
2 2 15 8 125 -30 to + 85 -55 to 150
kV
Tj Top Tstg
C C C
GND bumps (GND_H and GND_C - A3, D3 and E3) must be connected to ground on the printed circuit board for ESD testing and RF measurements.
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EMIF09-SD01F3 Table 3.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM IR = 1 mA VRM = 5 V per line
Characteristics Electrical characteristics (Tamb = 25 C)
Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between input and output Input capacitance per line Test conditions Min 6 50 Typ Max 20 200 Unit V nA
VCLVBR VRM IR IRM IRM IR V VRMVBR VCL I IPP
IPP
R1, R2, R3, R4, Tolerance 20% R5, R6, R7, R8, R9 R11, R12, Tolerance 30% R13, R14 R15 R21 Cline Tolerance 30% Tolerance 30% Vline = 0 V, VOSC = 30 mV, F = 1 MHz (under zero light conditions)
40
50 15 470 20
k k k pF
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Characteristics
EMIF09-SD01F3
Figure 3.
S21(dB) all lines attenuation measurement
Figure 4.
Analog cross talk measurement
dB
0.00
0.00 -10.00
dB
-10.00
-20.00
-20.00
-30.00 -40.00
-30.00
-50.00 -60.00
-40.00
F (Hz)
-50.00 100.0k 1.0M data0 data2 10.0M 100.0M data1 data3 1.0G
-70.00 -80.00 100.0k
F (Hz)
1.0M data0_data1 10.0M 100.0M 1.0G
Figure 5.
Digital crosstalk measurement
Figure 6.
ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (VIN) and on one output (VOUT)
Output Line 2
200mV/d
Vexternal=20V/d
Input Line 1
1V/d
10ns/d 5Gs/s
Vinternal =10V/d
100ns/d
Figure 7.
ESD response to IEC 61000-4-2 Figure 8. (-15 kV air discharge) on one input (VIN) and on one output (VOUT)
Cline (pF)
25
Line capacitance versus applied voltage
Vexternal=20V/d
20 15 10 5
F = 1 MHz VOSC = 30 mV Tj = 25C
Vinternal =10V/d
100ns/d
Vline (V)
0 0 2 4 6 8 10 12 14
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EMIF09-SD01F3
Application information
2
Application information
Figure 9. Aplac model
data0 Lbump Rbump Rline Rbump Lbump sddata0
MODEL = D1 Rsub
MODEL = D2
MODEL = D3
MODEL = D4
Rbump
Rbump
Rbump
Lbump
Lbump
Lbump
Rgnd
Rgnd
Rgnd
Lgnd
Lgnd
Lgnd
Figure 10. Aplac model variables
Variables aplacvar Rline 40 aplacvar C_d1 14.5p aplacvar C_d2 6.5p aplacvar C_d3 303p aplacvar C_d4 14.5p aplacvar Lbump 43pH aplacvar Rbump 17m aplacvar Cbump 150f aplacvar Lgnd 150pH aplacvar Rgnd 10m aplacvar Rsub 5 Diode D1 BV=7 IBV=1m CJO=C_d1 M=0.28 RS=1.13 VJ=0.6 TT=100n Diode D2 BV=7 IBV=1m CJO=C_d2 M=0.28 RS=0.8 VJ=0.6 TT=100n Diode D3 BV=7 IBV=1m CJO=C_d3 M=0.28 RS=0.37 VJ=0.6 TT=100n Diode D4 BV=7 IBV=1m CJO=C_d4 M=0.28 RS=1.13 VJ=0.6 TT=100n
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Ordering information scheme
EMIF09-SD01F3
3
Ordering information scheme
Figure 11. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10 (pF) or 2 letters = application 2 digits = version Package F = Flip Chip 3 = Lead-free, pitch = 400 m, bump = 255 m
yy
-
xx zz
F3
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 12. Package dimensions
400 m 40
400 m 40
255 m 40
605 m 55
185 m 10 m 1.97 mm 30 m
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1.97 mm 30 m
185 m 10 m
EMIF09-SD01F3
Ordering information
Figure 13. Footprint
Copper pad Diameter: 220 m recommended 260 m maximum Solder mask opening: 300 m minimum
Figure 14. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
E
Solder stencil opening : 220 m recommended
xxz y ww
Figure 15. Flip Chip tape and reel specifications
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
1.75 0.1 3.5 0.1
2.11
8 0.3
STE
STE
STE
xxz yww
xxz yww
xxz yww
All dimensions in mm
2.11
2.11
0.69 0.05
4 0.1
User direction of unreeling
Note:
More information is available in the application note: AN2348: "STMicroelectronics 400 micro-metre Flip Chip: Package description and recommendation for use" AN1751: EMI Filters: Recommendations and measurements
5
Ordering information
Table 4. Ordering information
Marking GZ Package Flip Chip Weight 5.2 mg Base qty 5000 Delivery mode Tape and reel (7")
Order code EMIF09-SD01F3
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Revision history
EMIF09-SD01F3
6
Revision history
Table 5.
Date 19-Oct-2005 09-Feb-2006 22-Mar-2006 28-Apr-2008
Document revision history
Revision 1 2 3 4 Initial release. Tape cavity dimensions added in Figure 13. Other graphics improved. Reformatted to current standard. Typical and maximum values updated for IRM in Electrical characteristics, page 3. Updated ECOPACK statement. Updated Figure 11, Figure 12 and Figure 15. Reformatted to current standards. Changes
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EMIF09-SD01F3
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